Field of the Invention
The present invention relates to a bus architecture communications scheme for enabling communications between a plurality devices or nodes in a computer system, and more particularly, to a dynamic, multi-speed bus architecture capable of performing data packet transfers at variable and upgradable speeds between fixed speed and multi-speed nodes.
Computer devices within a given computer system, such as a disk drive, a CRT, a printer and the like, need the ability to convey signals between themselves. In the past, this has been accomplished by means of a standard I/O bus which comprises a plurality of transmission lines and acts as a shared communications path for interconnecting several devices in the system. Hereinafter, all computer devices will be referred to as "nodes" for simplicity irregardless of whether or not the specific device has a higher intelligence otherwise known as a "local host". In addition, the term local host will be used irregardless of whether or not it comprises hardware or hardware and software.
In most bus architectures used today, each node in the system need only plug into the bus to be theoretically connected to each of the other nodes in the system. However, a data packet transmitted on this type of shared bus by a particular node is available for reception by all other nodes coupled to the bus such that the data packet transfers must be performed at a fixed speed based on the speed of the slowest node. Thus, the fixed speed of the data packet transfers on a particular bus must be defined prior to implementation of the bus itself since it is dependent upon the technological capability of the nodes at the time.
Hence, it would be desirable to implement a true dynamic, multi-speed bus having the capability of upward compatibility with newer and faster nodes while providing an optimum, cost-performance system implementation. As technology evolves rapidly, new nodes become available which are capable of significantly higher speeds than the nodes already implemented on a particular bus. In order to implement the newer, faster nodes in a computer system, one alternative is to create a new bus architecture (in addition to a new standard) each time the technology makes a new step. This is obviously quite an expensive solution. However, another alternative is to create a bus architecture in which new nodes can coexist with the old nodes. While less than optimal, this alternative is a lot more attractive from a practical point of view. Such new nodes will dearly have to operate at a reduced speed when communicating with older (and slower) nodes otherwise the older nodes will not be able to decode the data packets transferred on the bus. On the other hand, depending upon the bus topology, the higher speed nodes can communicate with other higher speed nodes at higher than the minimal speed, thus increasing the bus utilization. This upward compatibility requirement necessitates the development of a bus architecture that will accommodate speed upgrades with a minimum of complexity (minimum cost, minimum design effort and minimum upgrade time).
Another dimension to the problem of creating a dynamic, multi-speed bus having scalable speed transmission capabilities is cost. For a given technological level, the cost of a node is clearly a factor of its speed capability. There are very simple nodes which need to communicate on the bus only at a minimum speed such that the overall cost of the node is the most significant criterion (as opposed to the performance criterion). Examples of such nodes are a mouse, a keyboard, a microphone, etc. Clearly such nodes should not have to communicate at a speed faster than the minimum required transmission speed. At the same time, there exist on the bus very complex (and inherently expensive) nodes for which their performance is the significant criterion (as the cost of the communications channel of the bus becomes insignificant compared with the cost of the node itself). Examples of such nodes are a printer, a monitor, a computer, a high end storage node, etc. Such nodes need to communicate at significantly higher speeds than the minimum required transmission speed.
Therefore, in order for a bus to be able to accommodate various generations of nodes as well as nodes of varying cost ranges (and consequently of varying performance capabilities), it is desirable to provide a dynamic, multi-speed bus having the capability of upward compatibility with newer nodes able to operate at faster transmission speeds.
Accordingly, it is an object of the present invention to provide a method and apparatus for a scalable, multi-speed bus architecture which enables variable speed data packet transfers between newer, faster speed nodes and older, slower speed nodes coupled together via at least one variable speed, fixed size link forming a single interconnection of the multi-speed bus.
Another object of the present invention is to provide a method and apparatus for a scalable, multi-speed bus architecture in which the nodes coupled to the multi-speed bus comprise a novel interface architecture between the local hosts of the nodes and their connections to the multi-speed bus wherein the arrangement of the components of the interface greatly radiitares both design level and field level upgrades of the multi-speed bus and the nodes coupled thereto.
Another object of the present invention is to provide a method and apparatus for a transmit operation between nodes coupled together via a variable speed, fixed size link of a multi-speed bus in which a fixed speed, fixed size, variable length data packet transfer from a node's local host is converted into a fixed speed, variable size, variable length data packet transfer which is further converted into variable speed, fixed size, variable length data packet transfer for transmission on the link of the multi-speed bus.
A further object of the present invention is to provide a method and apparatus for a receive operation between nodes coupled together via a variable speed, fixed size link of a multi-speed bus in which a variable speed, fixed size, variable length data packet transfer from the link is converted into a fixed speed, variable size, variable length data packet transfer which is further converted into fixed speed, fixed size, variable length data packet transfer for reception by a local host of the receiving node.
Yet another object of the present invention is to provide a method and apparatus for a multi-speed bus architecture pursuant to the IEEE P1394 standard in which a physical channel interface chip and a link layer chip are coupled between a local host of a node and a multi-speed, serial bus for providing a fixed speed interface between the local host and the serial bus suitable for upward compatibility with faster nodes and the implementation of an isolation barrier therein.